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Testing current high density memory chips using older algorithms is highly time consuming. March test of O(n) is the most widely used approach for its high fault coverage and systematic way of extending the test sequences. Size of the March test is guided by the number of fault models. Most of the March test generation algorithms reported so far, takes long time especially in case of number of operations...
Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don't care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a genetic algorithm based heuristic to fill the don't cares. Our approach produces an average percentage improvement...
In recent years, power dissipation has emerged as the key issue not only for portable computers and mobile communication devices, but also for high-end systems. Reducing power dissipation is of primary importance in achieving longer battery life in portable devices. On the other hand, for high-end systems the cooling and packaging requirements are pushing the chip designers for low power alternatives...
This paper addresses the issue of blocking pattern selection to reduce both leakage and peak power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to circuit inputs. This though reduces dynamic power significantly, can result in quite an increase in the leakage power and peak power. We have presented a novel approach...
Power minimization is one of the very important issues in the testing of power constrained VLSI circuit. While existing literature emphasizes dynamic power reduction, leakage power is assuming more and more importance in the forthcoming technologies beyond 100 nm. This paper studies the effect of don't care filling of the patterns generated via automated test pattern generators, to make the patterns...
Due to higher switching activity within scan chain for scanning in/out of the stimuli/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places in the traditional scan chain, there by converting the D flip-flops...
Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC...
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