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In0.53Ga0.47As channel MOSFETs were fabricated on 300 mm Si substrate. The epitaxial In0.53Ga0.47As channel layer exhibits high Hall electron mobility comparable to those grown on lattice matched InP substrates. Excellent device characteristics (SS∼95 mV/dec., Ion/Ioff ∼105, DIBL ∼51 mV/V at Vds = 0.5V for Lg=150 nm device) with good uniformity across the wafer were demonstrated. The extracted high...
The air-sensitivity of the poly-Si interface in MOS transistors and its impact on the electrical properties are studied. It is found that the gate leakage localized near the side of air-exposed edges is possibly caused by air-induced degradation of the poly-Si interface, which supplies mobile NH3-like species to the gate edge side surface, resulting in the formation of a non-stoichiometric as well...
Layout versus Schematic (LVS) is a commonly used technique employed at the design stage to insure the correctness of physical layout. However, as process technologies continually advance, increasingly complex boolean operations are required to produce the desired on-mask patterns, which are frequently optimized to enhance transistor performance and process margin. Design layout which has been verified...
The ultra fine pitch micro bump became the future trend due to the development of 3D IC. In this research, three-dimensional simulation was employed to examine the temperature distribution in micro SnAg solder bumps. According to the result, the temperature distribution in solder bump of micro bump is nearly uniform. In addition, the hot side is near the substrate side, whereas the cold side is near...
We investigated the novel tandem thin film solar cell with nanoplate structure that can solve the conflict between the light absorption and the carrier transport in amorphous silicon thin film solar cell. This structure has n-type microcrystalline silicon nanoplate array on the substrate, and the p-layer and i-layer are sequentially grown along the surface of each n-type microcrystalline silicon nanoplate...
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