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This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature...
This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement...
Due to higher switching activity within scan chain for scanning in/out of the stimuli/response pair, during testing average and peak power dissipation is much higher than the normal mode operation of a circuit. In our paper we propose a method of reducing dynamic power consumption in scan chain by introducing XOR gate at selected places in the traditional scan chain, there by converting the D flip-flops...
Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. NoC has emerged as a new paradigm for designing core based System-on-Chip (SoC). The success of NoC design relies...
In today's system-on-chip (SOC) design process heterogeneous technology cores are integrated at several layers of hierarchy. Hence, multilevel test access mechanism (TAM) optimization is necessary for modular testing of hierarchical SOCs that contain earlier generation SOCs as embedded megacores. Unlike previous works that mostly assumes flat test hierarchy, the proposed technique considers the design...
Power has become one of the most important paradigms of design convergence for future microprocessor and ASIC/SOC designs. In this tutorial we present the importance of low power microprocessor/SOC design from the high level microarchitectural, RTL, gate level to transistor level design. We cover the conflicting goals of performance vs low power, routinely faced by designers today. Embedded microprocessor/SOC...
To handle large volume of test data required for testing a System-on-a-Chip (SoC) demands test data compression techniques. Again power consumption during testing is becoming a major concern. Our paper presents a method of reducing power taking into consideration the dictionary based compression technique proposed in literature, where indices of the dictionary are used for compressing test data. Paper...
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