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Compared to exhaustive testing, pseudo exhaustive testing requires a smaller test size and lesser test time. Dynamic power dissipation accounts for the major share of power dissipation in CMOS circuits. The amount of heat dissipated limits the density of a chip. The test mode power has been proved to be more than the functional power dissipation. In this work, we propose a method to identify the seed...
Among the power-aware circuit synthesis techniques that have been proposed so far, power-gating has traditionally been the most effective way to lower power. In this approach, power reduction is achieved by shutting off the power supply to some portions of the logic block which are not active. So, we have to partition the design into two or more power islands. Suitable Finite State Machine partitioning...
Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the...
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