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We present the concept of logarithmic computation for neural networks. We explore how logarithmic encoding of non-uniformly distributed weights and activations is preferred over linear encoding at resolutions of 4 bits and less. Logarithmic encoding enables networks to 1) achieve higher classification accuracies than fixed-point at low resolutions and 2) eliminate bulky digital multipliers. We demonstrate...
This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the...
We present matrix factorization as an enabling technique for analog-to-digital matrix multiplication (AD-MM). We show that factorization in the analog domain increases the total precision of AD-MM in precision-limited analog multiplication, reduces the number of analog-to-digital (A/D) conversions needed for overcomplete matrices, and avoids unneeded computations in the digital domain. Finally, we...
Modern massively parallel graphics cards (GPGPUs) offer a promise of dramatically reducing computation times of numerically-intensive data-parallel algorithms. As cards that are easily integrated into desktop PCs, they can bring computational power previously reserved for computer clusters to the office space. High performance rates make GPGPUs a very attractive target platform for scientific simulations...
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