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Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit,...
Circuit with double gates using independently controlled gates have been proposed to reduce the number of gates and to increase the logic densities per area. This paper introduces a vertical slit FET (double gate transistor) which has been demonstrated with the help of figures with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits...
In a pervasive sensor system, application entities may use the available infrastructure resources such as sensing devices, actuators, wireless modules and gateways to accomplish various tasks. For example, a group of humans/robots may use the infrastructure to track the current location of the group members. Many such tasks require a service which keeps track of the order of occurrence of events in...
Authors have in previous publications demonstrated the generation of SUM and DIFFERENCE patterns in a programmable phased array consisting of time-delay units. In this paper a few applications of such programmable phased array are highlighted. Delay-line cancellation method is revisited and it is shown that blind speed can be eliminated. Similarly some adaptive beam formation and interference rejection...
A method is developed for providing the optimal feedback gain matrix for high-order linear quadratic problems by a decentralized computational procedure. All the calculations in this approach are done off-line. The resulting gains are optimal for all initial conditions so that the eventual on-line computation is minimal. The method is applicable to both the regulator and the servomechanism problems...
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