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Among the power-aware circuit synthesis techniques that have been proposed so far, power-gating has traditionally been the most effective way to lower power. In this approach, power reduction is achieved by shutting off the power supply to some portions of the logic block which are not active. So, we have to partition the design into two or more power islands. Suitable Finite State Machine partitioning...
In this paper, a greedy approach for minimizing the area of a programmable logic array (PLA) using column folding of combinational component of finite state machines (FSMs) is presented. Also, the row reordering problem is addressed and a simple data structure is proposed to satisfy the constraints imposed by folding of columns. Genetic algorithm based formulation has been used for state encoding...
Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the...
State encoding is an essential step for sequential circuit synthesis, especially when area, delay and/or power consumption are the main emphasis. Sequential circuits consume a considerable amount of power, as these are used to implement control circuitry, which remains always active even when some of the data-paths are shutdown. With the rapid advancement in VLSI technology and device miniaturization...
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