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A bit-level pipelined 12-b×12-b two's complement multiplier with a 27-b accumulator has been designed and fabricated in a 1-μm CMOS technology. A novel quasi N-P domino logic structure has been adopted to increase the throughput, and special pipeline structures were used to reduce the latency significantly. The measured maximum clock rate is 140 MHz (i.e. 140 million multiply-accumulate...
The authors describe a continuous-time bandpass filter integrated in a 3- mu m CMOS technology, with an f/sub 0/ of 12.5 MHz and a 2% fractional bandwidth. The four-pole filter is modeled on two L-C resonators coupled by mutual inductance, resistively terminated at the input and output for maximum power transfer. Each resonator is simulated on the IC by two tunable integrators in negative feedback...
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