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This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz-10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18μm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at...
A 3.1-4.8GHz two-stage LNA for Group-1 UWB applications featuring current reuse, resistive feedback, complete and high ESD protection design is reported. ESD-RFIC co-design technique was used to ensure whole-chip optimization. The design is implemented in a foundry 0.18μm RFCMOS. Measurement shows a gain of 13.2dB/14.0dB, excellent input reflection of -13.4dB/-17.5dB, noise figure (NF) of 5.11dB/4...
A 3.1-4.8GHz LNA for lower-band UWB transceiver front-end ICs designed in a commercial 0.18μm CMOS is presented. The LNA features current reuse, resistive feedback, complete and robust full-chip ESD protection. LNA circuits with and without ESD protection are compared to minimize ESD-induced LNA performance degradation. Experiment shows a gain of 13.2dB, excellent input reflection of -13.4dB, NF of...
This paper reviews advances in new 3D electro-thermal modeling technique for ESD (electrostatic discharge) protection structures. New 3D ESD device modeling is critical to full-chip ESD protection circuit design synthesis, verification, optimization and prediction, especially for IC designs in sub 100 nm CMOS technologies.
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