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In this paper, wafer level and product level reliability characteristics of embedded DRAM technology with high-K dielectric Ta 2O5 MIM capacitors have been analyzed. It is found although hot carrier injection can induce more apparent gate-induced-drain-leakage (GIDL) current than off-state bias temperature (BT) stress docs, BT stress still dominate the failure bit count increase in real circuit operation...
In this paper, a new phenomenon regarding to failure bit count (FBC) distribution and data retention time of embedded DRAM with high-K dielectric Ta2O5 MIM capacitors has been observed and explored. Different from conventional knowledge with FBC increase or retention time reduction of DRAM after burn-in, it is found FBC decreased and retention time increased in the sub-0.1mum embedded DRAM technology...
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