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Power management and sensor driver integrated circuits need technologies with high breakdown voltage (BVdss), low on-resistance (Rsp) and preferably low process complexity and improved integration. A new 180nm High Voltage CMOS (HVCMOS) technology is described which includes LDMOS devices with 160V BVdss and an N-LDMOS device with minimum Rsp of 14.4mOhm·mm2 for 34V BVdss as part of a suite of LDMOS...
The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.
This paper describes a 180 nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.
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