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Dielectric breakdown in advanced gate stacks in state-of-the-art Si nanoelectronic devices has been one of the key front-end reliability concerns for further CMOS technology downscaling. In this paper, we present the latest findings in using physical analysis techniques such as transmission electron microscopy (TEM)/electron energy loss spectroscopy (EELS)/energy dispersive X-ray spectroscopy (EDS),...
Reliability study of high-κ (HK) gate dielectric based transistors has become imperative for the current and future CMOS technology nodes as the industry shifts towards replacement of conventional silicon oxynitride (SiON) with hafnium-based oxides. One of the key requirements of any oxide reliability study is a quantitative assessment of the time dependent dielectric breakdown (TDDB) lifetime using...
In order to achieve aggressive scaling of the equivalent oxide thickness (EOT) and simultaneously reduce leakage currents in logic devices, silicon-based oxides (SiON / SiO2) have been replaced by physically thicker high-κ transition metal oxide thin films by many manufacturers starting from the 45 nm technology node. CMOS process compatibility, integration and reliability are the key issues to address...
How can a metal-oxide-semiconductor (MOS) transistor suffer from multiple dielectric breakdowns (BD) with severe structural damages (e.g., local melting and metal migration) remain functional? Our results show that the amorphization of Si in the vicinity of the BD forms an effective p-n diode which prevents terminal short from happening when reverse-biased.
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