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Logic simulation provides SOC verification with full controllability and observability, but it suffers from very slow simulation speed for complex design. Using hardware emulation such as FPGA can have higher simulation speed. However, FPGA emulation approach has some limitations, i.e. unsynthesizable testbench and poor visibility for debugging. We address these problems by presenting a testbench...
The communication overhead between the software emulator in the workstation and the FPGA emulator is the speed bottleneck of the hardware acceleration platform. This paper presents a vector mode based hardware/software co-emulation methodology, which leverages the pipeline structure to transmit, receive and buffer data. This methodology reduces the communication overhead by carrying out a parallel...
Co-verification technologies are characterized by two inherently conflicting issues: signal observability and simulation performance. To overcome these limitations, we proposed a run-time RTL debugging methodology for FPGA-based co-simulation as well as debugging methodology for a FPGA emulator with testbench synthesis engine. The first method provides internal nodes probing on an event-driven co-simulation...
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