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In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve...
Many communications embedded systems implement decimation filters. In particular, base-band stage in multistandard receivers is composed of cascade of decimation filters performing channel selection. The number of used filter and the kind of these filters can have a significant impact on the computation complexity and power consumption of multistandard receivers. In This work we present FIR filters'...
The idea behind this work is to extract from a large number of FIR filter syntheses several curves that estimate the area and power consumption. The aim is to help filter designer to make the right choice regarding decimation factor versus area and power consumption. The performed experiences show that for a given filter order, the choice of the decimation factor has a deep impact on the area and...
Upgradeability and interoperability are main concerns of Software Defined Radio (SDR). But in the case of military applications, security is also a relevant aspect of SDR. The Secure Software Communication Architecture (SSCA) is a standardized solution to secure SDR. This architecture needs a cryptographic processor for security purposes. However, currently available SSCA compliant ASIC-based cryptoprocessors...
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