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The eSiGe layout effect induced by PC-bounded or STI-bounded eSiGe shows impact on device performance and variability increase. For PC-bounded device, performance degradation could be explained by the mobility loss due to reducing eSiGe volume and less stress strength. For STI-bounded device, performance degradation varies, due to strong interaction between eSiGe fill morphology and device overlap...
A novel NOR Flash cell with a build-in 2-bit capability consisting of two physically isolated ONO charge-storage nodes separated by an oxide dielectric in between over the channel region is demonstrated. This memory cell employs the virtual ground array architecture, much like NROM arrays, is sensed with the reverse read scheme. However, comparing to NROM, this novel cell offers a wider Vt window...
We present a detailed study of low-K/Cu structures under short duration pulse regime and establish a microscopic understanding of breakdown behavior under high current stressing. Random and anomalous behavior of the breakdown characteristics observed under very fast pulsing conditions are explained through electro-thermal instability. A model based on extensive experimental study has been developed...
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