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This paper, proposes a new architecture to reduce the silicon area of the Cartesian feedback (CFB) used to linearize a power amplifier in WCDMA communication standard. The first stage of the previous version consists of two CORDIC structures in vector mode for the phase computation following by a subtractor. Here, we propose to merge these two CORDIC structures to obtain directly the phase difference...
Many communications embedded systems implement decimation filters. In particular, base-band stage in multistandard receivers is composed of cascade of decimation filters performing channel selection. The number of used filter and the kind of these filters can have a significant impact on the computation complexity and power consumption of multistandard receivers. In This work we present FIR filters'...
The idea behind this work is to extract from a large number of FIR filter syntheses several curves that estimate the area and power consumption. The aim is to help filter designer to make the right choice regarding decimation factor versus area and power consumption. The performed experiences show that for a given filter order, the choice of the decimation factor has a deep impact on the area and...
This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex lowpass SigmaDelta modulator in multi-standard receiver. The proposed architecture fulfills the requirements of three standards: Wi-max, UMTS and GSM. The optimization of the proposed decimation structure leads to two implementation architectures which are optimized in different ways: area (in terms of...
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