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The idea behind this work is to extract from a large number of FIR filter syntheses several curves that estimate the area and power consumption. The aim is to help filter designer to make the right choice regarding decimation factor versus area and power consumption. The performed experiences show that for a given filter order, the choice of the decimation factor has a deep impact on the area and...
In this paper, we present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. Dual gate oxide co-integrated devices with EOT 17 ??/Vdd 1.1 V and 29 ??/Vdd 1.8 V are reported. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Delay improvement up to 15% is reported on Ring Oscillators...
This work presents a low-power multistandard decimation and channel selection filter architecture. The filter is suitable after an over-sampling sigma-delta converter and performs decimation in two stages. The first stage is a modified structure of the cascade of integrators-combs (CIC) filter and allows reducing sampling rate downto only the double of the Nyquist frequency. The second stage composed...
A compact digitally-controlled single-stage variable gain amplifier (VGA) is introduced, which doubles the dB-linear range through the reconfiguration, saves power by 50% while maintaining the same linearity performance compared to those of the previous design. Implemented in 0.18 mum CMOS technology, the 5-bit digitally-controlled VGA achieves dB-linear gain range of 42 dB (-21 to 21 dB) with gain...
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