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This brief presents an 8-bit 1-kS/s successive approximation register (SAR) analog-to-digital converter (ADC), which is targeted at distributed wireless sensor networks powered by energy harvesting. For such energy-constrained applications, it is imperative that the ADC employs ultralow supply voltages and minimizes power consumption. The 8-bit 1-kS/s ADC was designed and fabricated in 65-nm CMOS...
This paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power...
In this work, we present an analytical study of aliasing image spurs problem in digital-RF modulators. The inherent finite image rejection ratio of this types modulators is conceptually discussed. A pulse amplitude modulation (PAM) model of the converter is used in the theoretical discussion. Behavioral level simulation of the digital-RF converter model is included. Finite image rejection is a limiting...
In this paper, design of an asynchronous clockless delta modulator based analog-to-digital converter (ADC) is presented. The ADC employs level-crossing sampling technique. The ADC system is in the context of low speed smart dust sensor applications. For smart dust the benefit with continuous-time clockless system is its reduced hardware and lesser quantization noise power in the frequency band of...
An event-driven, clock-free analog-to-digital converter (ADC) based on a continuous-time delta modulation technique is presented in this work. The ADC output is a digital datum, continuous in time. The ADC system employs an unbuffered, area efficient segmented resistor-string digital-to-analog converter (DAC). Simulation results of the high level model of an 8-bit event-driven DM ADC system is presented...
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