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Established RF CMOS switch contains MOSFET in its main architecture with a 5.0 V of control voltage and required high value of resistance in circuitry of transceivers to detect the signal. To avoid the high value of control voltage and those resistances, we proposed a Double-Pole Four-Throw switch using RF CMOS technology and verified its performance interns of currents and switching speed. Also to...
In this paper, we have explored the designing approach of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs, for the wireless telecommunication systems to operate at the microwave frequency regime of the spectrum. This proposed CSDG MOSFET can be used as the RF switch for selecting the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the...
In this paper, we have designed a Double-Pole Four-Throw (DP4T) RF CMOS switch, using Double-Gate (DG) MOSFET which has a high dielectric Hafnium-dioxide (HfO2) in place of Silicon-dioxide (SiO2). The performance of HfO2 for the switch such as an effective ON-resistance, attenuation, flat-band capacitance, average dynamic power, doping densities, Debye length, and mobility of carriers, barrier heights...
In this paper, we have explored the design features of a Double-Pole Four-Throw (DP4T) RF CMOS switch with use of a novel Vertical Slit Field Effect Transistor (VSFET). This proposed switch circuit uses the double-gate which minimizes the number of transistors and increases the logic density of the transistor per unit area as compare to simple switch. These double gates are independently controlled...
In the wireless telecommunication systems, for increasing interest in RF switch using Complementary Metal Oxide Semiconductor (CMOS) technology, for high frequency is greatly integrated. In this paper, we use the Hafnium-dioxide material as dielectric substrate for designing a model of CMOS which is used for double-gate MOSFET in DP4T RF CMOS switch. This proposed model is compact and robust as well...
Elimination of the p-MOS transistor from the pass gate network significantly reduces the parasitic capacitances associated with each node in the circuit, thus, the operation speed is typically higher as compared to the CMOS counterpart. But then the improvement in the transient characteristics comes at the price of increased process complexity. In Complementary pass transistor logic (CPL) circuit,...
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward. The first component of capacitive parasitic, we will examine is the MOSFET capacitances. The classical approach for...
Circuit with double gates using independently controlled gates have been proposed to reduce the number of gates and to increase the logic densities per area. This paper introduces a vertical slit FET (double gate transistor) which has been demonstrated with the help of figures with unique independent double gate properties to demonstrate the possible advantages for independent double gate circuits...
In a pervasive sensor system, application entities may use the available infrastructure resources such as sensing devices, actuators, wireless modules and gateways to accomplish various tasks. For example, a group of humans/robots may use the infrastructure to track the current location of the group members. Many such tasks require a service which keeps track of the order of occurrence of events in...
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