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Interposer-based 2.5-D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed...
Modular test and hierarchical test of core-based System-on-Chip (SoC) are two widely used SoC test methodologies. In this paper, the hybrid test methodology that incorporates these two together is studied by using an industrial real case. Thorough experimental results are demonstrated to compare various scenarios of the hybrid hierarchical and modular tests for SoC designs. Based on the experimental...
Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents an efficient ExTest scheduling strategy that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the...
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