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We demonstrate a 300mm wafer scale conformal contact process to achieve uniform ultra-low specific contact resistivity (ρc) for metal/high-k/n+Si (MIS) contacts. To achieve conformal contacts, we use a sidewall TLM (STLM) test structure that helps to minimize current crowding effect and variability. A systematic study is provided by varying doping density (ND), high-k material (LaOx, ZrOx and TiOx...
This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm...
Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak Gm and IDsat, however also higher Ioff than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO2 gate and NiPtSi S/D...
Single-crystal SrTiO 3 has been grown on Si(100) using molecular beam epitaxy (MBE). The growth conditions, especially at the initial stage of nucleation, have a great impact on the SrTiO 3 /Si interface. A regrowth of an amorphous interfacial layer as thick as 23 9 has been observed and identified as a form of SiO x . This is a direct result of an internal oxidation during...
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