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This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm...
The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ∼25 nm, >1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation...
Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak Gm and IDsat, however also higher Ioff than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO2 gate and NiPtSi S/D...
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