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Embedded Delay Locked Loops (DLLs) and Phase Locked Loops (PLLs) are available as hard-macros in the latest Field Programmable Gate Arrays. The main features offered by DLLs and PLLs are clock phase de-skewing, frequency synthesis (multiplication or division) and jitter filtering. The clock signal at the output of a DLL or a PLL has a phase noise (or jitter), which has to be taken into account in...
The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM)...
The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been performed, one based on the phase information delivered by the VIRTEX-5 DCM and thus providing a...
The Dense Wavelength Division Multiplexing is an optical technology which allows transmitting across a fiber many wavelengths, which can be added and dropped by means of passive optical components. A plugin link module, capable of building full duplex nodes in the Gb/s domain for systems with real-time requirements, is presented in this paper. To debug and characterize the link, the module is plugged...
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