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We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the synopsys power compiler. The model, which from now on will be called Nos-HPM (Nostrum high-level power model) allows a fast power analysis and is accurate within 5%. System simulations with Nos-HPM run up to 500 times faster than with power compiler...
An on-chip communication network is most power efficient when it operates just below the saturation point. For any given traffic load the network can be operated in this region by adjusting frequency and voltage. For a deflective routing network we propose the design of a central controller for dynamic frequency and voltage scaling. Given history information including the load and frequency in the...
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making the implementation of these services entirely irrelevant for system design, an effective separation of system design from component design can be achieved. We discuss the principles to formulate network-on-chip services...
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