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Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The effects of threshold voltage and body contact are shown to significantly impact the SET response of advanced SOI technologies. Also, the reverse cumulative distribution is extracted from the count distribution for several targets and is shown...
Reliability-aware logic synthesis can be used to mitigate a circuit's response to radiation-induced soft errors. This paper analyzes the impact of using reliability-aware logic synthesis to reduce both the pulse width and the drain area of a circuit. Using our targeted cell library, several benchmark circuits were analyzed to identify equivalent, less-vulnerable implementations while minimizing penalties...
New heavy-ion data from a 130 nm bulk CMOS process shows a counterproductive result in using a common single-event charge collection mitigation technique. Guard bands can reduce single-event pulse widths for normal strikes, but increase them for angled strikes. Calibrated 3D TCAD mixed-mode modeling has identified a multiple-transistor charge collection mechanism that explains the experimental data,...
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