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FPGA Based design of area efficient router architecture for NoC is proposed in the present work. Design entry of the proposed router is done using Verilog Hardware Description Language (Verilog HDL). In the designed router four channels (east, west, north and south) are present. Each channel consists of first in first out (FIFO) buffers and multiplexers. Buffers are used to store data in binary form...
A novel hybrid eighteen-level inverter topology for open-end winding induction motor (IM) is presented in this paper. In the proposed topology one end of the open-end IM is fed by conventional two-level inverter, while other end is connected to a nine-level cascade H-bridge (CHB) inverter. The combined effect of these two inverters generates eighteen-level in the phase voltage of open-end winding...
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