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Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different...
In this paper we analyses the energy consumption of well known family of asynchronous circuits and present a new methodology for energy estimation of these circuits at intermediate-level of abstraction. Energy estimation is performed by simulating the intermediate format of the design. The number of Read and Write accesses on the ports of the concurrent processes are counted by analyzing the conditional...
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