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In wafer-scale CMOS image sensors, the 3-transistor structure suffers from its low speed. To overcome this limitation, we propose a digital pixel sensor which has a digital-pixel output instead of analog-pixel output as in a conventional 3-transistor pixel. The digital pixel sensor can provide a high frame because it eliminates analog-to-digital conversion time. In addition, it removes the noise from...
In this paper, we describe a programmable CAVLC decoder implemented with a video parsing coprocessor. The video parsing coprocessor is a VLIW processor that issues multiple instructions and supports condition-controlled instructions to efficiently program control intensive algorithms and customized instructions for bit operations and table matching. The complexity of the parsing coprocessor is 92...
An integrated switched beam forming network is demonstrated at V-band by integrating an absorptive single-pole four-throw (SP4T) switch together with a 4×4 Butler matrix using 0.13 μm CMOS process. The fabricated absorptive SP4T switch shows a measured insertion loss of 4.5 dB at 60 GHz and isolation higher than 31 dB from 57 to 63 GHz. The return losses of the deactivated output ports also maintain...
In this paper, a 10-Gb/s, 95-dBOmega, 20-mW optical receiver front-end is realized in a 0.13-mum CMOS technology for high speed serial interface. To guarantee 10-Gb/s operation using low cost photodiode, the effect of inherent photodiode parasitic capacitance should be suppressed. Thus, LC-ladder filter and modified common-gate amplifier is exploited as the input stage of pre amplifier. To enhance...
To highly isolate inherent parasitic capacitance (CPD) of photodiode, second-order passive LC-ladder network is exploited. And to enhance the bandwidth, various techniques, such as capacitive degeneration, inductive peaking, active feedback, and negative impedance compensation, are applied. In this paper, a 1.2-V 10-Gb/s optical receiver is designed in 0.13-mum CMOS technology. The proposed optical...
In this work, a 12-channel 120-Gb/s optical receiver array is realized in a 0.18-mum CMOS process. Optical receiver array consists of transimpedance amplifier (TIA) and limiting amplifier (LA). To enhance the bandwidth without deterioration of the other performance, advanced common-gate input configuration, active feedback technique, and negative impedance compensation are exploited. Post-layout simulations...
In this paper, a 12-channel 60-Gb/s differential transimpedance amplifier (TIA) and limiting amplifier (LA) array is realized in a 0.18-mum standard CMOS technology for the applications of hybrid optical printed-circuit boards (OPCBs). To relax the design tradeoffs of the TIA between the bandwidth and the large photodiode capacitance, we exploit the advanced common-gate input stage. And active feedback...
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