The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A virtual channel (VC) calculation algorithm for wormhole-switched on-chip networks is proposed. Traditionally, the virtual channels were allocated uniformly, which results in a waste of area and power. To remedy this situation, based on the queuing theory, we propose a router analytical model. Using this model, the proposed algorithm calculates the bandwidth usage at each router in the network according...
A new deadlock-free dynamic routing algorithm is proposed for wormhole-switched network-on-chip. Introducing the concept of multilevel congestion-aware mechanism which conveys more accurate feedback information about network congestion status than the DyAD routing, the proposed algorithm adopt proper routing algorithm to forward packets according to the current congestion level. Simulation results...
This paper introduces a novel CMOS-memristor hybrid reconfigurable architecture, mFPGA. Different from the existing crossbar-based CMOS-memristor architectures, mFPGA mainly consists of lTlM-like structures that can be fabricated by using a CMOS-compatible process. These devices can efficiently establish FPGA block memories. More importantly, novel CMOS-memristor routing switches are developed to...
In this paper, a novel reconfigurable architecture, cFPGA (CMOS-Nanorelay FPGA) is developed by integrating carbon nanorelays and CMOS devices to function as FPGA components. cFPGA is a highly efficient architecture, providing 2?? density and standby power improvement along with 30% dynamic power reduction as compared to the CMOS FPGA circuits. This performance improvement is achieved by using 2T1N...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.