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A sampling switch with an embedded Digital-to-Skew Converter (DSC) is presented in this paper. The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage. A similar bridged capacitors' charge sharing structure is used to minimize the area. The circuit is fabricated in a 0.18µm CMOS process and achieves sub-1ps resolution and 200ps timing range at a rate of 100MS/s...
The current-splitting architecture for the current-steering DAC can reduce the area of the current source array greatly. A background calibration technique for current-steering digital-to-analog (DAC) with the current-splitting array is presented. The proposed calibration technique can eliminate mismatch errors for both the upper bits array and the lower bits array in the background. A 14-bit current-steering...
A single-channel 1.0-GS/s 8-bit Voltage-Buffer-Free Pipelined-Folding-Interpolating analog-to-digital converter (PL-FAI-ADC) is presented. Grouped T/H blocks are adopted to cancel the voltage buffer between the T/H block and the pre-amplifiers array. A new full-digital T/H switch is proposed to cancel the bootstrapped capacitor, which can save the chip area grandly. An improved single-diode switch...
Temperature profile of K-shell emitting region has been measured by two spectrometers with high spectral resolution for azimuthally symmetric aluminum wire array implosions. Both spectrometers using spherically bent crystal analyer operated with spatial resolution. One of them was designed to capature broadband spectrum (4.4 Å–8.2 Å), and the other to realize profile distinguishing. Results on the...
A Nyquist-rate time-interleaved current-steering digital-to-analog converter (DAC) with dynamic channel matching (DCM) is proposed. Thanks to the proposed Nyquist-rate time-interleaved architecture, the DAC can properly operate at more than 1GS/s for a near-Nyquist output signal. The key limitation of the time-interleaved architecture is the mismatches between channels. The proposed DCM method can...
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