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A 14-bit 100-MS/s pipelined ADC in 0.18 mum 1P6M CMOS process is presented. A new sampling technique is introduced which achieves high linearity over wide bandwidth by eliminating the major sources of distortion at low and high input frequencies. The ADC uses digital background calibration, featuring a shuffled-dithering scheme, to obtain a DNL of +0.18/-0.18 LSB and an INL of +1.1/-0.6 LSB. It achieves...
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