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A novel PN diode decoding method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming...
An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device,...
Source/Drain (S/D) dopant concentration related reliability issues including erase speed degradation, sub-threshold swing (SS) increase, and program/erase (P/E) cycling induced low threshold voltage (VT) state drift and on-state current (ION) reduction are carefully examined in charge trapping (CT) NAND flash memories. Residual charges above S/D junctions has been identified as a dominant factor and...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
The present study investigates the charge trapping characteristics of Si-rich nitride thin films in detail by using the gate-sensing and channel-sensing (GSCS) method. Analytical results indicate that thicker (>7 nm) nitride thin films are fully-capturing; the trapped electrons are distributed in the center of the nitride, and the charge centroid is independent of the N/Si ratio. However, thinner...
Gene expression programming (GEP) is a powerful evolutionary algorithm derived from genetic algorithm and genetic programming. However, when dealing with complex problems, GEP shows quite slow convergence speed, it also probably encounters premature convergence. In this paper, gene expression-based clonal selection algorithm (GE-CSA) was proposed to synthesize combinational logic circuit, which combines...
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