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In this paper, a filter design guideline to reduce the ripple current in LLC resonant converters for the battery charger is proposed. The effect of filter inductor on the resonant network is mathematically analyzed, and a filter inductor is designed considering capacitance of the battery. The voltage gain of LLC resonant converter with filter inductor is analyzed through fundamental harmonic approximation...
This work proposes an 11b 70MHz CMOS pipelined A/D converter (ADC) as one of core circuit blocks for high-speed VDSL system applications. The proposed ADC for the internal use has the strictly limited number of externally connected I/O pins while the ADC employs on-chip CMOS current/voltage (I/V) references and a merged-capacitor switching (MCS) technique to improve ADC performances. The ADC implemented...
An experimental high performance 16M DRAM having 0.18 ??m design rule for giga bit DRAMs was developed. Junction leakage and junction capacitance was reduced by STI. Fast access time even at low operation voltage(~ 1.5V ) was achieved by TiSi2 gate, W-bit line, Ta2O5 capacitor, and new circuit techniques. Insufficient depth of focus margin for Back-End of Line process was overcome by triple metallization...
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