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We have first manufactured Complementary Tunnel-FETs (C-TFETs) in standard 12-inch CMOS foundry. With abrupt tunnel junction consideration for improved TFET performance, technology of monolithically integrating C-TFET with CMOS is developed. Planar Si C-TFET inverter is also demonstrated, indicating a new electrical isolation requirement between neighboring devices for practical C-TFET integration...
Two novel silicon-based TFETs are discussed and experimentally demonstrated, including JTFET and mFSB-TFET, through junction engineering and gate configuration design for steeper SS, on-current enhancement, which shows higher potentials in low power circuits.
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