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Multi-threaded processors interleave the execution of several threads to reduce processor stalling time. Instruction cache misses usually account for a significant fraction of the overall stalling time due to frequent instruction fetches. Apart from incurring extended execution time (hence its direct impact on energy consumption), cache misses also lead to indirect power overheads and increased thread...
Energy consumption is a critical issue in embedded systems design. One way of being energy efficient is to complete the execution as early as possible. Multi-threaded processors reduce the execution time by exploiting both the instruction level and thread level parallelism, and offer an effective solution for energy saving. With a typical multi-threaded processor design, whenever the instruction pipeline...
Multi-threaded processor designs enable high performance of a single processor core by exploiting both the thread-level and instruction-level parallelism. The performance gain is, however, at the cost of increasing energy consumption, which is not desirable to embedded systems. This paper investigates the energy efficiency of varied multi-threaded processor designs (with the coarse-grained and fine-grained...
This paper presents a bus coding methodology for instruction memory data-bus switching reduction. Compared to the existing state of the art multi-way partial bus-invert coding (MPBI) which relies on data bit-correlation, our approach is very effective in reducing switching activity for bus data, since little correlation can be observed on instruction data buses. Our experiments demonstrate the proposed...
The design and construction of a repetitive high-current pulsed accelerator-TPG700 is described in this paper. The accelerator consists of a Tesla transformer with 40 ohm build-in coaxial pulse forming line. The triggered high-pressure switch of TPG700 has the capability of conducting current of 17.5kA in 35ns' duration at 100 pps. The transformer was designed to operate at 1.4MV, when its primary...
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