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Hold-time faults are gaining attention in modern technologies because of process variation, power supply noise, and etc. A path-based hold-time fault model is proposed to cover short paths to and from every flip-flop. In addition, the number of faults is linear to the number of flip-flops in the circuit. Two-timeframe circuit models are proposed for ATPG and fault simulation. We show that traditional...
A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware...
This work proposes a novel dual-channel 3D NAND Flash that exhibits both n-channel and p-channel NAND characteristics. The NAND is junction-free without dopant inside the array. Unlike the conventional 3D NAND, the drain side near SSL is N+ doped junction, while source side near GSL is P+ junction. A positive pass-gate read voltage (Vpass, r) induces n-type virtual source/drain for the center WL's,...
In a complex sequential circuit, the problem of fixing min-delay violations becomes more and more important. To our knowledge, no efficient approach is proposed to eliminate the min-delay violations in a layout-level implementation. In this paper, the min-delay violations in a layout-level implementation are considered. By using the available space along the routing wires, redundant loads can be inserted...
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