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A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The output frequency of...
A digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration is presented. The proposed bandwidth calibration circuit adjusts the proportional and integral gain of the digital loop filter to tolerate the process, voltage and temperature (PVT) variations. This BBPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0049 mm2 and the power is 3.34 mW from a supply of 1.1 V. The...
An all digital phase-locked loop with a frequency range of 2.35 ∼ 2.55 GHz is presented. A MASH 1-1-1 ΔΣ time-digital converter is used to quantize phase errors. High resolution and third-order noise-shaping are achieved simultaneously. A digitally controlled oscillator with three-stage tuning bank is used to realize wide frequency range and high frequency resolution. A prototype integrated in 130nm...
This paper reports on the design and characterization of a low phase noise MEMS oscillator with ultra-low polarization voltage. An innovative oscillation circuitry is also proposed by a high gain-bandwidth, low-power TIVA (trans-impedance voltage amplifier) which is composed of two stages: the I-to-V stage and voltage gain stage. The TIVA is fabricated using 1P6M 0.18 μm CMOS technology and has been...
A digitally controlled oscillator (DCO) that achieves a minimum frequency tuning step of 20 kHz without any dithering is presented. Three tuning stages are employed to obtain a wide frequency range of 1 GHz in the classical LC tank. The fine tuning bank is realized by inverse connection of two pairs of pMOS transistors and a tiny unit capacitance of 0.47 fF is achieved. A prototype integrated in 130nm...
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