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In the context of SRAM testing, we propose a methodology to define proper conditions under which SRAMs should be tested to improve their reliability. This methodology is especially suitable to deal with the impact of threshold voltage variability affecting SRAM core-cell transistors. By establishing an objective manner of comparing different test conditions, the proposed study shows how it is possible...
At-speed scan testing has become mandatory due to the extreme CMOS technology scaling. The two main at-speed scan testing schemes are namely Launch-Off-Shift (LOS) and Launch-Off-Capture (LOC). As it can be easily implemented, LOC has been widely investigated in the literature in the last few years, especially regarding test power consumption. Conversely, LOS has received much less attention. In this...
At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling...
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