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This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach...
This paper presents a comprehensive framework for logic diagnosis consisting of two main phases. In the first phase, a set of suspected faulty sites is obtained by applying an approach based on an Effect-Cause analysis. Then, in the second phase, a set of realistic fault models is associated with each suspected faulty site by analyzing specific information, called fault evidences, collected during...
This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach...
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