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This paper presents a novel pipelined FFT/IFFT processor for OFDM applications. The proposed architecture employs a low-complexity complex multiplier and a constant complex multiplier to eliminate the need of ROM tables, thus consumes lower power than the existing works. Finally, this design spends about 33.6K gates, and the power consumption is about 9.8mW at 20MHz.
This work applies perfect-shuffle on software defined radio's bit-shuffling blocks, such as puncturer and interleaver, which data alignment issue is also investigated. A demonstration of such algorithm on IEEE 802.11a (WiFi) standard is implemented with Texas Instruments® intrinsic perfect-shuffle and inverse perfect-shuffle instructions combined with ANSI C on a TMS320 C64x digital signal processor...
The task of efficient implementation of bit-serial scrambler algorithms on a word-parallel software defined radio micro-architecture is considered. By exploiting properties of the exclusive-OR Boolean logic operator, a novel power-of-two look-ahead recursive algorithm transformation method is developed. Together with loop-unrolling, this new method produces an efficient vector scrambler algorithm...
An instruction set architecture independent design method targeted on embedded software defined radio is proposed. Without the aid of specified instructions, this work focuses on cycle-efficient implementation of bit-oriented operations on word-based processors. High portability between platforms is achieved and demonstrated with an IEEE 802.11a (WiFi) transmitter implemented in C language on both...
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