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i-FinFET, an evolutionary FinFET design, offers better short channel performance. In this work, the scaling characteristics of the iFinFET and FinFET are studied using 3D TCAD simulations based on their ION/IOFF ratio. It is found that the better performance in iFinFET is achieved only below certain gate length. The gate length below which the iFinFET shows better performance is called optimal gate...
Semiconductor industry has explored various novel device structures to extend CMOS scaling. Circular geometry devices have been recently proposed to improve immunity to short channel effects without compromising planarity. In this work, one such circular geometry device called RingFET is considered and its performance enhancement through Lightly Doped Drain (LDD) implantation is sought using 3D TCAD...
In this paper, we have analyzed the performance enhancement of reconfigurable field effect transistor (RFET) using gate workfunction, inter-gate length and inter-gate dielectric permittivity through TCAD simulations. The parameters, ON current, OFF current and ION/IOFF ratio are extracted from the saturated ID-VG characteristics. When the inter-gate length is varied, enhanced ION/IOFF ratio is achieved...
In this paper, the performance investigation of Gate-Inside (GI), Gate-Outside (GO) cylindrical Junction-less Silicon Nanotube Field Effect Transistor (JLSiNT) devices and comparative analysis with Gate-Inside & Outside (GIO) JLSiNT device are done using 3D TCAD numerical simulations. ON current (ION), OFF current (IOFF), Sub-threshold Swing (SS), Threshold voltage (VTH), Trans-conductance (gm...
In this paper, the effect of three device parameters, gate electrode work function (WF), device layer/film thickness (Tc) and channel doping concentration (Nd), on DC parameters has been studied in 20 nm gate length Bulk Planar Junctionless Transistor (BPJLT) using Sentaurus TCAD simulator. Using the above device parameters (ION/IOFF) ratio of the BPJLT is optimized with IOFF constraint. The results...
The Structure of n type junctionless Tunnel FET is created and its characteristic is studied using TCAD simulations. The device simulations have been implemented with different voltage levels for different gate structures present in the device-gate over drain (VG1) and gate over source (VG2), and the transfer characteristics (ID-VG) are studied. Considering drive current (Ion)> off current (Ioff...
Recent years has shown a growing interest in the development of change detection techniques for the analysis of Intrusion Detection. Current research shows that change detection methods can be used for a wide range of real time applications. Detecting the changes by observing data collected at different times is one of the most important applications of network security because they can provide analysis...
In this paper, typical floating gate flash memory is simulated and studied using independent gate junction-less FET. TCAD simulator is used for generating the memory structure as well as for studying its programming, erasing and reading behaviour. Programming and erasing delays are 1.6 ms and 1.53 ms respectively for 25 nm fin width device. Programming and erasing voltages are +9 V and −15 V respectively...
This paper investigates the effect of process variations on unity gain frequency (ft) in 30 nm gate length FinFET by performing extensive 3D TCAD simulations. Sensitivity of ft on different geometrical parameters, channel doping, source/drain doping and gate electrode work function are studied. It is found that ft is more sensitive to gate length, underlap, gate oxide thickness, source/drain doping...
In this paper, the effect of device geometry variations on a narrow band cascoded low noise amplifier (LNA) structure performance has been studied in 30 nm gate length FinFET-based LNA operating at 10 GHz using device and mixed mode simulations in Sentaurus TCAD simulator from Synopsys. Twelve different device geometrical parameters are varied to capture their impact on LNA parameters. It is found...
Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the extent of design exploration. In this work, we propose a fast, accurate Monte-Carlo based model for predicting processor performance. We apply this technique to predict the CPI of in-order architectures and validate it against the Itanium-2...
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