The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We demonstrate a cost effective 65-nm SOTB CMOS technology for ultra-low leakage applications. Novel single p+poly-Si/Hf/SiON gate stack of mid-gap work function and precise GIDL control achieved ultra-low leakage of 0.2 pA/µm, which corresponds to approx. 100nA/chip (100k gate logic). Now the SOTB technology can provide three options from ultra-low voltage to ultra-low leakage that covers a wide...
We demonstrate high performance Ge n-MOSFETs with novel raised source/drain fabricated on high quality single crystal Ge selectively grown heteroepitaxially on Si using Multiple Hydrogen Anealing for Heteroepitaxy(MHAH) technique. Until now low source/drain series resistance in Ge n-MOSFETs has been a highly challenging problem. Source and drain are formed by implant-free, in-situ doping process for...
We successfully demonstrate Ge pMOSFET integrated on Si. In this process, Ge is grown selectively on Si on patterned SiO2 by heteroepitaxy, and pMOSFET is fabricated with gate dielectric stack consisting of thin GeO2 and Al2O3 and Al metal gate electrode. Fabricated devices show ~80% enhancement over the Si universal hole mobility. These results are promising toward monolithically integrating Ge MOSFETs...
We developed an application specific multi-processor generation system intended for realtime applications. In this system, we adopted a distributed memory type multi-processor architecture with hierarchical tree network as a configurable multiprocessor which can be adapted to various scale systems flexibly. We have also developed a configurable multi-processor prototype as LSI chips with the 0.18...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.