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Information Flow Tracking (IFT) provides a formal methodology for modeling and reasoning about security properties related to integrity, confidentiality, and logical side channel. Recently, IFT has been employed for secure hardware design and verification. However, existing hardware IFT techniques either require designers to rewrite their hardware specifications in a new language or do not scale to...
Secure hardware design is a challenging task due to the fact that security properties are difficult or impossible to model and subsequently verify using traditional hardware design tools. The "state of the art" for hardware design security relies heavily on functional verification, manual inspection, and code review to identify security vulnerabilities. This labor intensive process significantly...
Cryptographic function implementations are known to leak information about private keys through timing information. By using statistical analysis of the variations in runtime required to encrypt different messages, an attacker can relatively easily determine the key with high probability. There are many mitigation techniques to combat these side channels; however, there are limited metrics available...
Hardware-based side channels are known to expose hard-to-detect security holes enabling attackers to get a foothold into the system to perform malicious activities. Despite this fact, security is rarely accounted for in hardware design flows. As a result, security holes are often only identified after significant damage has been inflicted. Recently, gate level information flow tracking (GLIFT) has...
Flight control, banking, medical, and other high assurance systems have a strict requirement on correct operation. Fundamental to this is the enforcement of non-interference where particular subsystems should not affect one another. In an effort to help guarantee this policy, recent work has emerged with tracking information flows at the hardware level. This article uses a specific method known as...
One I2C protocol design method for reusability was proposed. In this method, design was divided into 3 levels: protocol level, signal level and interface level. Protocol level can be reused without any modification. Signal level can be reused by setting the number of be transferred byte according to specific operation. Interface level can be reused by changing the number of operation mode and the...
An energy-efficient data collection protocol for wireless sensor network based on tree (EEDCP-TB) is proposed in this paper. EEDCP-TB constructs data collection tree through the method of flooding avoidance and use the cascading timing scheme to allocate aggregation time in order to save node's energy; further more, this protocol introduce the node energy state parameter to meet energy balance to...
The aim of this study is to develop a MR compatible PET that is insertable to MRI and allows simultaneous PET and MR imaging of human brain. The brain PET having 72 detector modules arranged in a ring of 330 mm diameter was designed. Each PET module composed of 4 ? 4 matrix of 3 mm ? 3 mm ? 20 mm LYSO crystals coupled to a tileable 4 ? 4 array Geigermode avalanche photodiode (GAPD) and designed to...
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