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This paper presents key design techniques and challenges in implementing one of the first integrated, energy-efficient 60 GHz transceivers including baseband circuitry. The 90 nm CMOS direct-conversion design operates from a 1.2 V supply and has been optimized for 5-to-10 Gb/s QPSK modulation centered at 60 GHz. To achieve power consumption of 170 mW in transmit mode and 138 mW in receive mode, this...
This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each...
A low power inductorless wideband variable gain control amplifier (VGA) for baseband receivers has been designed in a standard digital 90 nm CMOS technology. The VGA was implemented using four-stage modified Cherry-Hooper amplifier with a dual feedback DC-offset canceling network, which simultaneously corrects DC offsets and extends bandwidth without a peaking inductor resulting in saving the chip...
In this paper, a highly integrated receiver front-end is demonstrated that is manufactured in a digital CMOS process using a design approach amenable to mass production. Unlike many previous attempts in CMOS, the results of the design are well predicted by the simulation results, matching the desired frequency band and the simulated gain to a very high accuracy. Low noise and high gain are demonstrated...
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