The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a physics-based picture that predicts the scaling of...
High temperature RTO (Rapid Thermal Oxidation) process can get good quality but growth rate was too fast to get a controllable ultra-thin SiO2 as interfacial layer (IL) for high-K gate dielectrics application. In this paper, we investigated the physical and electrical properties of IL film obtained by different oxidation gas ratio, temperature, pressure. We found high temperature (>1080C) and hydrogen...
We have developed a low leakage and highly reliable SiON gate dielectrics by using novel low temperature deposition of chlorine-enriched silicon nitride upon a thin oxide. This method can achieve higher top-to-bottom nitrogen concentration ratio and keep nitrogen peak toward top surface. It was found that the low temperature Si3N4 deposition technique can form a high nitrogen percentage SiON (>...
We have investigated the precursor effect of La2O3 cap layers on Vfb tuning and EOT reduction in SiO2/HfO2/TiN gate stacks. The Vfb tuning and EOT reduction correlate with the intermixing of La2O3 and HfO2 dielectrics which forms dipoles at the lower interface between HfO2 and SiO2 IL and the diffusion of La and Hf atoms to the SiO2 IL. The use of La(fAMD)3 precursor for the La2O3 cap layer deposition...
The behavior of barrier engineered charge trapping devices incorporating Al2O3 and HfO2 high-K layers has been critically examined. We propose to use a thicker buffer oxide (≫ 6 nm) and thin (≪5nm) high-K top capping layer for BE-MAONOS and BE-MHONOS in order to improve the reliability. Thinner high-K top capping layer reduces the fast initial charge loss under high-temperature baking. Moreover, it...
Silicon-on-lattice engineered substrates (SOLES) are SOI substrates with embedded Ge layers that facilitate III-V compound integration for advanced integrated circuits. The new materials integration scheme in SOLES requires the analysis of its thermal stability and diffusion barrier properties. In this study, we report on the successful monolithic integration of CMOS/III-V transistors with a reduced...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.