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This paper presents a method towards automatic structural synthesis of analog multiplier based on a hierarchical topology "super-topology", which is abstracted from the most standard four-quadrant multipliers. The essential components in the super-topology are four identical cells, which consist of several MOS-transistors and determine features and performances of multipliers. We build all...
This paper presents a method of design automation for analog circuits, focusing on topology generation and quick performance evaluation. First we describe mechanisms to generate circuit topologies with hierarchical blocks. Those blocks are specialized by adding terminal information. The connection between blocks is in compliance with a set of synthesis rules, which are extracted from typical schematics...
This paper presents a method of design automation for analog circuits, focusing on topology generation and quick performance evaluation. First we describe a new mechanism to generate circuit topologies with hierarchical blocks, which are specialized by additional terminal information. The connection between blocks is in compliance with a set of synthesis rules, which are extracted from typical schematics...
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