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In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have...
The photoresist SU-8, often used in microtechnology, has been acoustically characterized at a frequency of 1 GHz thanks to thin-disk piezoelectric ZnO transducers. Acoustical characterization of SU-8-based nanocomposites made of SU-8 and nanosize TiO2 and/or SrTiO3 particles is presented. These nanocomposite materials would be used to achieve acoustical matching between silicon and water at a frequency...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
In this work, we designed and fabricated two types of double-gated isolated vertically aligned carbon nanofiber field emission arrays (VACNF FEAs) to study how the tip position relative to the gate affects the device performance. In the first type, the tip is in-plane with the gate, and in the second type, the tip is 0.9 mum below the gate. To quantify the effectiveness of the two gates to affect...
A scalable poly-Si/AlN/HfSiO gate stack, implementing a new aluminum nitride (AlN) cap layer, combined with oxygen diffusion barrier, halo and counter doping engineering, high temperature spike anneal for gate and junction activation, and optional inverted gate implant, has been successfully developed to fully offset the large threshold voltage (Vt) shifts in poly-Si/HfSiO devices and achieve good...
FinFET devices are demonstrated with multiple fins (>2) at a 120nm pitch using e-beam lithography to address some key challenges of FINFETs for 32nm node technologies and beyond. Target Vt's are achieved by proper halo design using 20nm fins. Vt scatter due to Fin width variation is greatly reduced with a reduced halo. When such a realistic fin pitch is used, S/D contact formation becomes a serious...
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