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A learning environment based on Microsoft Excel spreadsheets is presented allowing for fast and systematic exploration of different implementations of integer adder designs. The spreadsheet properties are exploited to illustrate both layout and timing properties of an adder design. The usefulness of the learning environment is demonstrated by several different examples. We also describe how the spread-sheet...
When performing narrow-width computations, power gating of unused arithmetic circuit portions can significantly reduce leakage power. We deploy coarse-grain power gating in 32-bit integer arithmetic circuits that frequently will operate on narrow-width data. Our contributions include a design framework that automatically implements coarse-grain power-gated arithmetic circuits considering a narrow-width...
We propose a high-speed and energy-efficient two-cycle multiply-accumulate (MAC) architecture that supports two's complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product generation circuitry and a reduction tree, while the second stage, thanks to a special sign-extension solution, implements all other functionality...
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