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This paper presents a 40-Gb/s transmitter (TX) and receiver (RX) chipset for chip-to-chip communications in a 65-nm CMOS process. The TX implements a quarter-rate multi-multiplexer (MUX)-based four-tap feed-forward equalizer (FFE), where a charge-sharing-effect elimination technique is introduced into the 4:1 MUX to optimize its jitter performance and power efficiency. The RX employs a two-stage continuous-time...
A high-speed distributed vibration sensor based on balanced Mach-Zehnder interference and optical time-domain reflectometer is introduced to distinguish multiple vibration simultaneously. The experimental results show a high spatial resolution and a fast frequency response.
The inductively coupled coil in wireless power transfer (WPT) system is the key to optimizing the power transfer efficiency. Based on an iterative printed spiral coil (PSC) design procedure, this paper proposes a load-based design method to improve the efficiency stability for a load-variable system. The efficiency stability coefficient is defined to choose the optimal PSCs. Several pairs of PSCs...
An 80 Gb/s 4-level pulse amplitude modulation (PAM4) wireline receiver is presented in this paper. This receiver adopts quarter rate architecture to improve data rate and reduce power consumption. In order to reduce the complexity of the clock and data recovery (CDR) design, a voltage control oscillator (VCO) based CDR without reference clock is used. Furthermore, four BBPDs are used to sample the...
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain. A two stage pseudodifferential inverter based ring VCO with...
In this paper, we introduce a real-time pressure measurement system. A soft material with gauge points is placed ahead of a micro camera, and the material's deformation reflects the pressure applied on it. The image processing circuit mainly consists of an image pre-processing module, a connected area labeled module and a centroid coordinate calculation module. Experiments are implemented to demonstrate...
This paper describes the design of a serial-link transceiver that supports various communication standards from 1.25 to 12.5Gb/s, implemented in 40nm CMOS technology. Both DC and AC coupling mode can be provided by the receiver, in which a wide range PI-based CDR is also proposed. The transceiver utilizes a 3-tap FFE, a 2-stage CTLE and an adaptive 2-tap DFE to achieve the compensation for a Nyquist...
The 10Gbase-KR protocol is widely used to accomplish the high speed data conversion in the Ethernet area. This paper presents a design of the critical controller in the physical coding sublayer based on the 10Gbase-KR. In order to satisfy the demand of the high speed data conversion, the scrambler and descrambler are specially designed to work in a parallel mode. The post-synthesis simulation results...
This paper proposed the architecture of a linear current-mode CMOS image sensor integrated parallel processing unit enabling various block-level calculation during the read-out procedure. Combinational logic with two scanning DFF chains and global control signals as input generates the output to address the right pixels with high flexibility. Four current conveyors are used to perform CDS function...
A 10 GHz 4-phase ring-VCO based injection-locked clock multiplier (RILCM) for 40 Gb/s SerDes application is presented in this paper. The RILCM adopts two loops which share common part circuit to realize the injection lock. The first loop which is the frequency lock loop (FLL), drags the VCO's free-running frequency to the injection lock-in range. Another loop which is the injection timing control...
IEEE 802.11b WLAN is widely used to implement Wi-Fi based Time Difference of Arrival (TDoA) indoor localization. This paper presents a novel IEEE 802.11b baseband receiver and the corresponding localization system. Frame detector and phase recovery block are dedicated to frame reception and frequency offset compensation. Baker code re-correlator is specially designed to improve anti-noise performance...
This paper presents a 40–80 Gb/s quarter rate PAM4 wireline transmitter. The transmitter incorporates a 2-tap feed-forward equalizer (FFE) based on multiple-multiplex (MUX) and a parallel PRBS7 generator. The transmitter is achieved in 65nm CMOS technology and supplied with 1.2V. The simulation results show that the proposed transmitter can work at 40–80 Gb/s with 4-level pulse amplitude modulation...
Received Signal Strength Indicator (RSSI) is simplest among various indoor localization methods. The main drawback is requiring a training phase to build fingerprints database, which is time consuming and sensitive to changes of test environment. Time based approaches such as Time of Arrival (ToA) and Time Difference of Arrival (TDoA) achieve better performance with some hardware expenditure, while...
This paper presents a wideband LC PLL designed for multi-protocol serial link applications. Dual LC voltage controlled oscillator (VCO) cores are used to cover a wide frequency range while keeping a high Q factor of the LC tank, and multi-ratio dividers are used to satisfy the multi-protocol requirements. Each LC VCO adopts a 4-bit switch capacitor to increase the frequency tuning range and decrease...
A serial-link repeater chip with a single stage continuous-time linear equalizer (CTLE) and a 3-tap feedforward equalizer (FFE) is realized in a 0.13μm SiGe BiCMOS technology. The CTLE with the negative capacitance circuits is implemented to achieve a larger high-frequency boosting at the receiver side. By utilizing the LC-based delay elements, the FFE accomplishes the transmitter de-emphasis without...
In order to improve the throughput of error correction decoding for the high-performance solid-state drives (SSDs), a semi-parallel low-density parity-check (LDPC) decoding architecture is proposed in this paper. The circuit of the LDPC decoder which can be dynamically configured with bit rate and code length is implemented using the scheduling control flow mode of single instruction multiple data...
This article presents a new method of using barometric chips to make tactile array sensor for manipulator. The barometric chip can detect and convert analog air pressure to digital signal and calculate the value of surface air pressure. First we design appropriate circuits with the PCB technology and mount the chips on the board, then we manufacture a silica gel air cell on each chip. In the way,...
This paper proposed a novel scheme which gives mathematical description of 2D/3D measurement and includes two visual detection strategies with switching method by Hu moment. On the six degree of freedom serial robot, a rigid planar patch is overlaid as auxiliary measuring. In view of improve computing efficiency and robustness, a preprocess stage of the scheme based on visual attention mechanism is...
This paper is concerned with the stability of sampled-data system with sensor and actuator saturations using discontinuous Lyapunov functional approach. The system measurements are sampled and then transmitted to dynamic output-feedback controller, and a closed-loop system is modeled as an interval time-varying delay control system with nonlinear items. Through constructing discontinuous Lyapunov...
This paper presents an iteration self-adapting color image enhancement algorithm to extract visual attention focus in accuracy. Initially, the color space should be translated from RGB to YCbCr where the iteration image enhancement model is deduced in constrain of chroma and hue. The subsequence image evaluation function implements closed-up control to adjust the iteration step and enhancement performance...
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