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A potential drain/source swap problem in a traditional low-leakage charge pump under low supply is investigated and the design methodology and results of a low-voltage CMOS charge pump structure for phase-locked loop (PLL) applications are presented. Simulated in a 65-nm CMOS process, the structure is capable of reducing the static leakage current to the pA range while providing close to rail-to-rail...
Recursive polyphase cascaded integrator-comb (CIC) prefilters are proposed to greatly increase the speed of digital decimation so as to address demands of high speed sigma-delta ADCs that over-sample at several GHz. The recursive computations in the new method avoid the substantial area/complexity increases in traditional polyphase decomposition implementations. Clock rate improvements by factors...
Parallel cascaded integrator-comb (CIC) pre-filters are proposed to greatly increase the speed of digital decimation filters. Several times of clock rate improvement can be achieved by paralleling computations. Unlike traditional poly-phase parallel decomposition, the new method avoids the substantial area/complexity increase, as a consequence of converting to parallel structure, by exploiting the...
A new architecture for the implementation of very high speed digital decimation filters is described. It combines the cascaded integrator-comb (CIC) multirate filter structure with filter sharpening techniques to improve the filter's passband response. A SPT-encoded non-recursive technique is further applied to realize parallel computation and improve the maximum clock rate of the filter. With a 0...
To address the problem of current source output impedance degradation in a large full-scale sub-ranging ADC's reference ladder, a feedback closed-loop negative supply system, occupying 0.028 mm2 in 0.18-mum CMOS, is proposed. This system can be applied to overcome headroom issues in other high-performance large-dynamic-range analog circuits such as large input swing continuous-time filters, analog...
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